1. Field of the Invention
The present invention relates to a voltage regulator circuit applied to an IC for driving a liquid crystal panel used in a mobile telephone, a digital camera or the like.
2. Description of Related Art
A liquid crystal panel driving IC used in a mobile telephone, a digital camera or the like is increasingly made faster in transmission of data (as high-speed serial transmission) and smaller in size. Due to this, the liquid crystal panel driving IC is often designed by a fine and low voltage process (hereinafter, referred to as “the low voltage process”) capable of using higher-speed and smaller-sized elements. In such a low voltage process, a voltage with which an element is broken down (withstand voltage of the element) necessarily falls. It is, therefore, required to pay attention to the range of a voltage to be used.
Furthermore, a power supply voltage (battery voltage) supplied from a power supply (battery) to the liquid crystal panel driving IC is often higher than the voltage used in such a low voltage process. Due to this, it is required to use the power supply voltage after regulating the voltage to an appropriate voltage using a voltage regulator circuit included in the liquid crystal panel driving IC.
Moreover, in a normal case, the power supply voltage is stabilized by a device (such as a stabilization circuit) arranged between the power supply and the liquid crystal panel driving IC, and is supplied to the liquid crystal panel driving IC as a supply voltage as a supply voltage. However, not only an average consumption current but also an instantaneous consumption current is desired to be as low as possible for the liquid crystal panel driving IC since the stabilization circuit includes such a function a's a function to prevent overcurrent.
FIG. 1 shows a configuration of a general voltage regulator circuit 110 (hereinafter, referred to as “the voltage regulator circuit 110”). The voltage regulator circuit 110 includes a differential amplifier circuit AMP1, a first resistor element R1 (hereinafter, “the resistor element R1”), and a second resistor element R2 (hereinafter, “the resistor element R2”).
The differential amplifier circuit AMP1 is connected to a high-voltage power supply [VDD] supplying a high voltage VDD and a low-voltage power supply [VSS] supplying a low-voltage VSS (ground voltage GND) lower than the high-voltage VDD, and operates with the voltage between the high-voltage VDD and the low-voltage VSS. The differential amplifier circuit AMP1 includes a positive-side input terminal +IN that is a first input terminal, a negative-side input terminal −IN that is a second input terminal, and an output terminal. A reference voltage Vref is supplied to the positive-input terminal +IN as the supply voltage.
One end of the resistor element R1 is connected to the output terminal of the differential amplifier circuit AMP1. One end of the resistor element R2 is connected to the other end of the resistor element R1, and the other end of the resistor element R2 is connected to the low-voltage power supply [VSS]. One end of the resistor element R2 is also connected to the negative-side input terminal −IN via a signal line. One end of a smoothing capacitor C1 is connected to the output terminal of the differential amplifier circuit AMP1 and one end of the resistor element R1 via an output node, and the other end of the smoothing capacitor C1 is connected to the low-voltage power supply [VSS].
The resistor elements R1 and R2 divide an output voltage Vout100 output from the differential amplifier circuit AMP1 into voltages to generate a divided voltage Vmon100 on one end of the resistor element R2. The differential amplifier circuit AMP1 amplifies the difference between the reference voltage Vref supplied to the positive-side input terminal +IN and the divided voltage Vmon100 supplied to the negative-side input terminal −IN. The smoothing capacitor C1 smoothes the output voltage Vout100 output from the differential amplifier circuit AMP1.
FIG. 2 shows a configuration of the differential amplifier circuit AMP1. The differential amplifier circuit AMP1 includes first and second N channel MOS (Metal Oxide Semiconductor) transistors MN1 and MN2 (hereinafter, referred to as “the transistors MN1 and MN2”), first to third P channel MOS transistors MP1, MP2, and MP3 (hereinafter, referred to as “the transistors MP1, MP2, and MP3”), and first and second constant current sources.
Sources of the transistors MN1 and MN2 are connected to one node in common. Gates of the transistors MN1 and MN2 are used as the negative-side input terminal −IN and the positive-side input terminal +IN of the differential amplifier circuit AMP, respectively.
A first constant current source is provided between the sources of the transistors MN1 and MN2 and the low-voltage power supply [VSS]. For example, the first constant current source is a third N channel MOS transistor MN3 (hereinafter, referred to as “the transistor MN3”). The sources of the transistors MN1 and MN2 are connected to the drain of the transistor MN3, and the low-voltage power supply [VSS] is connected to the source thereof. A bias voltage Vbias is supplied to the gate of the transistor MN3 for turning on the transistor MN3.
Sources of the transistors MP1 and MP2 are connected to the high-voltage power supply [VDD] in common, gates thereof are connected to one node in common, and drains thereof are connected to drains of the transistors MN1 and MN2, respectively. The gate of the transistor MP1 is connected to the drain of the transistor MN1.
The source of the transistor MP3 is connected to the high-voltage power supply [VDD], the gate thereof is connected to the drain of the transistor MN2, and the drain thereof is connected to one end of the resistor element R1.
A second constant current source is provided between the drain of the transistor MP3 and the low-voltage power supply [VSS]. For example, the second constant current source is a fourth N channel MOS transistor MN4 (hereinafter, referred to as “the transistor MN4”). The drain of the transistor MP3 is connected to the drain of the transistor MN4 and the low-voltage power supply [VSS] is connected to the source thereof. The bias voltage Vbias is supplied to the gate of the transistor MN4 for turning on the transistor MN4.
Next, operation performed by the voltage regulator circuit 110 will be described below.
The reference voltage Vref is supplied to the positive-side input terminal +IN of the differential amplifier circuit AMP1, and the divided voltage Vmon100 is supplied to the negative-side input terminal −IN of the differential amplifier circuit AMP1. Due to this, the differential amplifier circuit AMP1 operates so that the voltage supplied to the negative-side input terminal −IN is equal to that supplied to the positive-side input terminal +IN, that is, equal to the reference voltage Vref.
If Vref>Vmon100 (namely, if the output voltage Vout100 is lower than a voltage-of-interest), then an ON-resistance of the transistor MP3 falls, and a current I100 falls in the smoothing capacitor C1 via the differential amplifier circuit AMP1 from the high-voltage power supply [VDD]. As a result, the output voltage Vout100 rises. If Vref<Vmon100 (if the output voltage Vout100 is higher than the voltage-of-interest), then the ON-resistance of the transistor MP3 rises, and a current Isink flows in the transistor MN4 included in the differential amplifier circuit AMP1 from the smoothing capacitor C1. As a result, the output voltage Vout falls. By repeating this operation, the output voltage Vout100 is made constant to the voltage-of-interest. In this case, the output voltage Vout100=voltage-of-interest is represented by the following Equation.Vout=Vref×(R1+R2)/R2